The ever increasing demand for memory storage capacity has pushed the capacity of memory devices significantly beyond 1 Gbit. Accordingly, memory elements of a memory device are required to either store and retain a minimal number of charges (e.g., fewer than 100 electrons per memory element), or sense a small change in a structural property of the memory element, such as resistivity, all with very low power consumption. In addition, memory elements must also be scalable to very high densities with a low fabrication cost. Further, in the near future, a memory element must also allow multilevel (stacking or multiple sensing levels) processing of memory cells. One of the memory elements that can meet these requirements is a recently developed nonvolatile nanotube (NVNT) switch, which is a type of resistivity memory.
One technology well suiting to meet these ever increasing demands is resistive change memory, often referred to as resistance RAMs by those skilled in the art. Such devices and arrays include, but are not limited to, phase change memory, solid electrolyte memory, metal oxide resistance memory, and carbon nanotube memory such as NRAM™.
Resistive change memory devices and arrays store information by adjusting a resistive change memory element, typically including some material that can be adjusted between a number of non-volatile resistive states in response to some applied stimuli, within each individual memory cell between two or more resistive states. For example, each resistive state within a resistive change memory cell can correspond to a data value which can be programmed and read back by supporting circuitry within the device or array.
For example, a resistive memory change element might be arranged to switch between two resistive states: a high resistive state (which might correspond to a logic “0”) and a low resistive state (which might correspond to a logic “1”). In this way, a resistive change memory element can be used to store one binary digit (bit) of data. In another example, a resistive change memory element might be arranged to switch between four non-volatile resistive states, allowing a single cell to store two bits of information.
U.S. patent application Ser. No. 11/280,786 to Bertin et al., incorporated herein by reference, teaches the fabrication of such a resistive change memory element. As taught by Bertin, a two terminal nanotube switching device may be employed as a resistive change memory element. Such a nanotube switching device includes a first and second conductive terminals and a nanotube article. The nanotube article overlaps a portion of each of the first and second conductive terminals. In at least some embodiments taught by Bertin, the nanotube article is a nanotube fabric layer disposed over the first conductive terminal. In such embodiments the second conductive terminal is disposed over the nanotube fabric layer, forming a three layer device with the nanotube fabric layer substantially between the first and second conductive elements.
Bertin further teaches methods for adjusting the resistivity of the nanotube fabric layer between a plurality of nonvolatile resistive states. In at least one embodiment, electrical stimuli is applied to at least one of the first and second conductive elements so as to pass an electric current through said nanotube fabric layer. By carefully controlling these electrical stimuli within a certain set of predetermined parameters (as described by Bertin in Ser. No. 11/280,786) the resistivity of the nanotube fabric layer can be repeatedly switched between a relatively high resistive state and relatively low resistive state. In certain embodiments, these high and low resistive states can be used to store a digital bit of data (that is, a logic “1” or a logic “0”).
Nanotube articles (such as those referenced by Bertin) may be realized through the formation and patterning of nanotube fabric layers and films. For example, U.S. Pat. No. 7,334,395 to Ward et al., incorporated herein by reference in its entirety, teaches a plurality of methods for forming nanotube fabric layers and films on a substrate element using preformed nanotubes. The methods include, but are not limited to, spin coating (wherein a solution of nanotubes is deposited on a substrate which is then spun to evenly distribute said solution across the surface of said substrate), spray coating (wherein a plurality of nanotube are suspended within an aerosol solution which is then dispersed over a substrate), and dip coating (wherein a plurality of nanotubes are suspended in a solution and a substrate element is lowered into the solution and then removed). Further, U.S. Pat. No. 7,375,369 to Sen et al., incorporated herein by reference in its entirety, and U.S. patent application Ser. No. 11/304,315 to Ghenciu et al., incorporated herein by reference in its entirety, teach nanotube solutions well suited for forming a nanotube fabric layer over a substrate element via a spin coating process.